1. Field of the Invention
The present invention relates to a semiconductor memory device in which sub-memories such as SRAM (static RAM) are used as cache memory on the same semiconductor substrate as is formed the main memory such as DRAM, and in which it is possible to configure bi-directional data transfer bus lines between the main memory and sub-memory. In particular, it relates to redundancy configurations for performing defect recovery in the main memory.
2. Description of the Related Art
Generally, memory devices (main memory) used by computer systems are relatively slow, inexpensive semiconductor devices with large capacities, and quite often the general-purpose DRAM (dynamic RAM) does not meet user demands. In recent years, in order to speed up the computer systems (especially speed up the MPU), attempts have been made to speed up the DRAM forming the main memory. However, since it alone is not enough to speed up the MPU (microprocessor unit), it has become common practice to configure a high-speed memory region as sub-memory between the MPU and the main memory. High speed SRAM (static RAM) and ECLRAM (emitter coupled logic RAM) have been commonly used for this type of sub-memory, which is also referred to as cache memory.
This sub-memory can be mounted outside of the MPU or can be internalized in the MPU, however, semiconductors having the main memory formed from DRAM and the sub-memory formed from SRAM mounted on the same semiconductor substrate have been noticed recently, for example, as shown in Japanese Patent Application No. Hei 11-64094 (Japanese Patent Application Laid-open No. 2000-260197). With the conventional technology in this semiconductor memory device, data transfer bus lines are used to connect the memory cell arrays of the sub-memory and the memory cell array of the main memory and via these data transfer bus lines it is possible to directly connect the main memory and sub-memory.
This type of semiconductor memory device will now be briefly summarized while referencing FIG. 2. The semiconductor memory device shown in FIG. 2 is comprised of main memory-memory cell arrays 110-1 to 110-4, which form the main memory, and sub-memory-memory cell arrays 120-1 and 120-2, which form the sub-memory, and contains a xc3x978 bit synchronous interface. In this example, main memory is formed into two banks, main memory-memory cell array 110-1 and main memory-memory cell array 110-4 form bank A, and main memory-memory cell array 110-2 and main memory-memory cell array 110-3 form bank B.
In addition, 512 data transfer bus lines TBL (TBL1 to TBL512) are configured crossing main memory-memory cell arrays 110-1 and 110-2, and sub-memory-memory cell array 120-1. These data transfer bus lines TBL facilitate the transfer of data between the main memory-memory cell clusters and sub-memory-memory cell clusters, so that, data in, for example, one column of sub-memory cell clusters can be transferred to four columns of main memory cell clusters via one data transfer bus line. Data transfer bus lines TBL (TBL513 to TBL1024) are configured in the same manner, crossing main memory-memory cell arrays 110-3 and 110-4, and sub-memory-memory cell array 120-2. In this example 1024 bits of transfer data can be transferred via data transfer bus lines TBL1 to TBL1024 at one time.
It should be noted here that in the semiconductor memory device formed with the configuration mentioned above, there are redundant memory cell arrays formed in each of the respective main memory-memory cell arrays and sub-memory-memory cell arrays. Data transfer bus lines connect memory cell clusters in the redundant main memory-memory cell arrays and memory cell clusters in the redundant sub-memory-memory cell arrays, in the same manner as the normal memory cell clusters are connected.
Furthermore, when performing defect recovery in the main memory-memory cell array, the memory cell clusters travel along the data transfer bus lines as units, so that each memory cell cluster of the main memory-memory cell arrays and sub-memory-memory cell arrays are substituted by the redundant memory cell cluster in one lump.
However, according to this technique, in order for the memory cell clusters traveling along data transfer bus lines to be replaced, all of the redundant memory cell clusters traveling along the transfer data bus lines are used for as little as one spot of defect recovery, leading to a low rate of recovery.
The present invention, in consideration of the above problems, aims to provide a semiconductor device that can use redundant memory cell clusters along data transfer bus lines to recover a plurality of defects with an improved rate of recovery.
In order to solve the above problems, the present invention has the following structures. Namely, the semiconductor memory device according to claim 1 of the present invention is a semiconductor memory device comprised of main memory (for example, the component corresponding to main memory 101, described below), sub-memory (for example, the component corresponding to sub-memory 102, described below), and data transfer bus lines (for example, the components corresponding to data transfer bus lines TBL, described below), which are configured so that bi-directional data transfer can occur between said main memory and said sub-memory via said data transfer bus lines. This semiconductor memory device is further comprised of a redundant circuit, which, during a read-out or write operation, determines an address to be replaced, by referencing the main memory address (for example, the signal component corresponding to main memory row selecting signal DXn, described below) corresponding to certain designated external data in the sub-memory, and then performs defect recovery for defects located in said main memory based on said resultant determination. This redundant circuit is comprised of, for example, the components corresponding to redundant main memory-memory cell array DMAR, redundant data transfer bus lines TBLR1 and TBLR2, redundant sub-memory-memory cell array SMAR, redundant global data input/output lines GIOR, redundant data input/output lines SIOR, redundant data input line connection circuits 155R1 and 155R2, redundant read/write amplifier 153R, and address-substituting determination circuits 2001 and 2002, described below.
Furthermore, the semiconductor memory device according to claim 2 of the present invention, is a semiconductor memory device comprised of a main memory (for example the component corresponding to main memory 101, described below), a sub-memory (for example the component corresponding to sub-memory 102, described below) and a plurality of data transfer bus lines (for example the component corresponding to data transfer bus lines TBL, described below), which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory. This semiconductor memory device is further comprised of a redundant circuit, which determines an address to be substituted based on an address (for example the signal component corresponding to sub-memory column selecting signal SYm, described below) designated in said sub-memory by an external component during either read-out or writing and an address in said main memory (for example the signal component corresponding to main memory row selecting signal DXn, described below), which corresponds to said address, and then performs defect recovery for defects located in said main memory based on the result of said determination. This redundant circuit is comprised of, for example, the components corresponding to redundant main memory-memory cell array DMAR, redundant data transfer bus lines TBLR1 and TBLR2, redundant sub-memory-memory cell array SMAR, redundant global data input/output lines GIOR, redundant data input/output lines SILR, redundant data input line connection circuits 155R1 and 155R2, redundant read/write amplifier 153R, and address-substituting determination circuits 2001 and 2002, described below.
Furthermore, in the semiconductor device according to claim 3 of the present invention is the semiconductor memory device mentioned in any of claims 1 and 2, the said redundant circuit is comprised of at least one redundant main memory-memory cell array (for example, the component corresponding to redundant main memory-memory cell array DMAR, described below) formed in said main memory; at least one redundant sub-memory-memory cell array (for example, the component corresponding to redundant sub-memory-memory cell array SMAR, described below) formed in said sub-memory; redundant transfer data bus lines (for example the component corresponding to redundant data transfer bus lines TBLR1 and TBLR2, described below), which connect said redundant main memory-memory cell array and said redundant sub-memory-memory cell array, and which are configured so that data can be transferred bi-directionally between said redundant main memory-memory cell array and said redundant sub-memory-memory cell array; and, at least one address-substituting determination element (for example the component corresponding to address-substituting determination circuits 2001 and 2002, described below), which determines said address to be substituted. This redundant circuit selects said redundant sub-memory-memory cell array based on the result of said determination by said address-substituting determination element.
Furthermore, the semiconductor memory device according to claim 4 of the present invention is the semiconductor memory device mentioned in any of claims 1 through 3 wherein said address in main memory is a memory cell cluster formed in said main memory, which shares said data transfer bus lines, and is divided into a plurality of groups, and which is an address (for example, the signal components corresponding to main memory row selecting signal DXn, bank selecting signal BS, and segment selecting signals SEG1 to SEG4, described below) which designates one of said plurality of groups.
Furthermore, the semiconductor memory device according to claim 5 of the present invention, is the semiconductor memory device mentioned in claim 4, wherein said main memory address is an address (for example the signal component corresponding to main memory row selecting signal DXn, described below), which selects a certain row in said main memory.
Furthermore, the semiconductor memory device claim 6 of the present invention is the semiconductor memory device mentioned in claim 4, wherein said main memory address is an address (for example the signal component corresponding to bank selecting signal BS, described below), which selects a certain row in said main memory.
Furthermore, the semiconductor memory device according to claim 7 of the present invention is the semiconductor memory device mentioned in claim 4, wherein said main memory address is an address (for example the signal component corresponding to segment selecting signals SEG1 to SEG4, described later), which selects a certain segment in said memory.
The semiconductor memory device according to claim 8 of the present invention is the semiconductor memory device mentioned in any of claims 1 through 7, which is further comprised of a hold circuit (for example the component corresponding to main memory address information hold circuit 3000, described below), which holds said main memory address and supplies said main memory address to said redundant circuit.